1. Field of the Invention
The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten.
2. Description of the Prior Art
A cache may be arranged to store data and/or instructions fetched from a memory so that they are subsequently readily accessible by a processor. Hereafter, the term xe2x80x9cdata valuexe2x80x9d will be used to refer to both instructions and data. The cache will store the data value until it is overwritten by a data value for a new location required by the processor. The data value is stored in cache using either physical or virtual memory locations. Should the data value in the cache have been altered then it is usual to ensure that the altered data value is re-written to the memory, either at the time the data is altered or when the data value in the cache is overwritten.
A number of different configurations have been developed for organising the contents of a cache. One such configuration is the so-called high associative cache. In an example 16 Kbyte high associative cache such as the 64-way set associative cache 30 illustrated in FIG. 1A, each of the 64 ways 110 contains a number of cache lines 130. Data values associated with a particular virtual address can be stored in a particular cache line of any of the 64 ways 110 (i.e. there are 64 choices of location for that data value within the cache 30). Each such group of 64 cache lines is referred to as a set. Each way 110 stores 256 bytes (16 Kbyte cache/64 ways). If each cache line stores eight 32-bit words then there are 32 bytes/cache line (8 wordsxc3x974 bytes/word) and 8 cache lines in each way ((256 bytes/way)/(32 bytes/cache line)).
Another such configuration is the so-called low associative cache. In an example 16 Kbyte low associative cache such as the 4-way set associative cache 30xe2x80x2 illustrated in FIG. 1B, each of the 4 ways 140, 142, 144, 146 contain a number of cache lines 130. Data values associated with a particular virtual address can be stored in a particular cache line of any of the 4 ways (i.e. each set has 4 cache lines). Each way stores 4 Kbytes (16 Kbyte cache/4 ways). If each cache line stores eight 32-bit words then there are 32 bytes/cache line (8 wordsxc3x974 bytes/word) and 128 cache lines in each way ((4 Kbytes/way)/(32 bytes/cache line)).
A data value stored in the cache may be overwritten to allow a data value for a new location requested by the processor to be stored. If the data value overwritten is then required for a subsequent operation it must be re-fetched from the main memory which may take a number of clock cycles. Hence, when it is known that certain data values stored in the cache will be required for a future operation it is useful to designate those data values stored in the cache as locked to prevent those data values from being overwritten, this technique often being referred to as xe2x80x9clockdownxe2x80x9d. By locking the data value it is possible to ensure that the data value will be in the cache when it is required, which provides, for example, predictability of access times for real-time code.
FIG. 2 illustrates one such lockdown technique of the 4-way set associative cache 30xe2x80x2 described above which utilises a cache controller 20. The cache controller 20 selects one of the four ways 140, 142, 144, 146 in the cache 30xe2x80x2 to store the fetched data value. Typically, when storing data values in the cache, a so-called xe2x80x9clinefillxe2x80x9d technique is used whereby a complete cache line of, for example, 8 words (32 bytes) will be fetched and stored. The cache controller 20 comprises a locked way register 22 and force bit flag 24. The locked way register 22 determines the number of ways 140, 142, 144, 146 that are used to store locked data. If data values are to be locked in the cache, the force bit flag 24 is set, whereas if data values are not to be locked in the cache, the force bit flag 24 is reset.
When a data value is to be stored in the cache 30xe2x80x2, the cache controller 20 will determine the status of the locked way register 22 and force bit flag 24. If the force bit flag 24 is not set then cache controller 20 will select one of the unlocked ways and the data value is stored in a suitable location in the unlocked way.
However, when lockdown is required the locked way register 22 is set to select the way to be locked and the force bit flag 24 is set. Now that the force bit flag 24 is set the cache controller 20 selects the locked way in dependence on the contents of the locked way register 22 and the data value is stored in a suitable location within the locked way. For example, assuming the locked way register 22 contains a value xe2x80x9c0xe2x80x9d, line fills of locked data values will occur in way 0. Once lockdown is complete, the locked way register is incremented, in this example to contain a value xe2x80x9c1xe2x80x9d, and the force bit flag 24 is reset. Data values stored in way 0 are now locked. Any further data values to be stored will be placed in ways 1 to 3. Should further data values need to be locked in the cache, the force bit flag 24 is set and line fills of locked data values will then occur in way 1. Again, once lockdown is complete, the locked way register is incremented, in this example to contain a value xe2x80x9c2xe2x80x9d, and the force bit flag 24 is reset. Data values stored in way 0 and way 1 are now locked.
As described above, should data values need to be stored in an unlocked way, the cache controller 20 will select one of the remaining unlocked ways for fetched data to be stored thereafter. Hence, lockdown is achieved and the locked data values cannot be overwritten without the force bit flag 24 being set.
Whilst the lockdown technique described above allows lockdown, this approach has a number of disadvantages.
Firstly, it is clear that this technique is not very flexible as during lockdown sequential ways are filled with locked data values and hence, for example, if way 1 contains locked data values, way 0 cannot be arranged to store unlocked data values without way 1 also being so arranged.
Secondly, the lockdown technique requires a dedicated lockdown program to carefully manage the storage of data values in the lockdown way to ensure that parts of the lockdown program do not get locked in the lockdown way along with the data. Having the lockdown program or parts thereof occupying the lockdown way is clearly undesirable as this will result in incorrect operation of the lockdown process. Hence, the lockdown program will either need to be written such that it resides in an area of so-called xe2x80x9cuncacheablexe2x80x9d memory such that the lockdown program does not get locked in the cache, or will have to be pre-loaded into another cache way prior to performing the lockdown process. Furthermore, when the dedicated program is forced to operate from memory, its operation is comparatively slow.
Hence, there is a need to provide an improved lockdown technique.
According to a first aspect of the present invention there is provided a data processing apparatus comprising a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers, each lockdown controller being associated with a corresponding way, each lockdown controller comprising an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way.
In accordance with embodiments of the present invention, only data values whose addresses identifiers fall within the address range specified by the processor will be locked by the lockdown controller into the corresponding way during the lockdown mode.
This technique provides for reduced complexity during lockdown because in preferred embodiments a dedicated lockdown program is not required to carefully manage the storage of locked data values in the cache, and instead locking of data values can occur automatically. In an n-way set associative cache memory of preferred embodiments, one or more of the lockdown controllers may receive an address range for use in a lockdown mode. When a data value to be cached is received, the cache selects one of the available ways to store the data value. When lockdown is required, the processor will instruct the lockdown controller associated with a corresponding way to enter the lockdown mode. Thereafter, data values whose address identifier is within the address range of the lockdown controller will be stored and locked down in the corresponding way. Should the address identifier not fall within the address range of the lockdown controller then the data values will be stored in one of the other ways.
However, if a lockdown program is still used in embodiments of the present invention, then the restrictions placed upon the programmer when writing the program are reduced as he need not be concerned that the program will accidentally be locked in the lockdown way of the cache. All the programmer need do is to ensure that the address identifiers of the lockdown program instructions and data do not fall within the address range specified to the lockdown controller. By this simple measure, it can be ensured that the data values of the lockdown program will not occupy the lockdown way and prevent the correct operation of the lockdown program. In particular, there is no requirement that the lockdown program be written such that it resides in an area of so-called xe2x80x9cuncacheablexe2x80x9d memory, or be pre-loaded into another cache way prior to performing the lockdown process.
This technique also provides for increased flexibility since a lockdown controller may store an address range for lockdown, but lockdown is only initiated when the processor selects the lockdown mode. Hence, lockdown may be initiated or terminated as and when required.
Preferably, each lockdown controller further comprises a mode indicator for identifying when the lockdown mode has been selected for the corresponding way.
In preferred embodiments, the mode indicator provides information about the mode selected for the corresponding way, since each way may preferably operate in a number of different modes. In preferred embodiments, the mode indicator will, therefore, enable a determination to be made as to whether the corresponding way is available to store all data values, unavailable to store any data values or only available to store locked data values.
Preferably, the mode indicator comprises an enable lockdown flag, the lockdown mode being selected when the enable lockdown flag is set by the processor.
In preferred embodiments, when the enable lockdown flag is set, data values whose address identifier is within the address range will be locked into the corresponding way. When the lockdown flag is not set, the lockdown controller will generally operate in an unlocked mode where any data values may be stored in the corresponding way.
Optionally, the mode indicator further comprises a disable unlocked allocation flag, the corresponding way being prevented from storing any unlocked data values when the disable unlocked allocation flag is set.
Hence, when the disable unlocked allocation flag is not set, the corresponding way may be available to store any data values. However, when the disable unlocked allocation flag is set, the corresponding way is prevented from storing any further unlocked data values.
In embodiments which include both the enable lockdown flag and the disable unlocked allocation flag the following modes can occur in the corresponding way: any data values to be stored (enable lockdown flag not set, disable unlocked allocation flag not set); no data values to be stored (enable lockdown flag not set, disable unlocked allocation flag set); only locked data values to be stored (enable lockdown flag set, disable unlocked allocation flag set).
Preferably, the number of addresses in the address range equals the number of entries in the corresponding way.
Hence, the entire selected way may be utilised and completely filled with locked data.
Alternatively, the number of addresses in the address range is less than the number of entries in the corresponding way.
Hence, a narrower range of addresses may be locked into part of the selected way.
It will be appreciated by the skilled person that with the above technique a complete way must be designated as locked, thus reducing the size of the available cache. Whilst this may not be particularly problematic for a high associative cache, for a low associative cache, such as that described above, a significant amount of the cache becomes unusable (e.g. a quarter in the FIG. 1B example).
Preferably, therefore, the cache further comprises a lockdown field for each entry which is set to indicate that the one or more data values in that entry are locked.
Hence, each data value may be individually designated as locked, and because the lockdown field is set, the cache will not overwrite the locked data values with unlocked data values. Accordingly, in such preferred embodiments, there is no need to set the disable unlocked allocation flag, since each locked data value is marked as such by the setting of the corresponding lockdown field, and so cannot be overwritten by any unlocked data placed in that way. Once the desired data values have been locked in the corresponding way, the enable lockdown flag may be cleared to prevent further data values which fall within the address range from overwriting the locked data.
This approach allows locked and unlocked data values to share the same way of a cache which helps improve cache utilisation. Because a complete way need not be designated as locked this increases the size of the available cache for unlocked data values. This approach is particularly advantageous for low associative caches, where each way is a significant proportion of the overall cache.
Preferably, each data value comprises a cache line and the lockdown field comprises one bit.
Hence, a complete cache line may be designated as locked by simply utilising one bit.
Viewed from a second aspect, the present invention provides a lockdown controller for a data processing apparatus in accordance with the first aspect of the present invention, the lockdown controller comprising an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way.
According to another aspect of the present invention there is provided a method of locking data values in a way of an n-way set associative cache, the cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the method comprising the steps of a) selecting a way to operate in a lockdown mode, b) storing an address range specified by a processor in an address register of a lockdown controller associated with the way selected at step (a), and c) upon receipt of a data value at the cache, locking the data value in the way selected at step (a) if the corresponding address identifier is within the address range.